In recent years, for a design of an LSI, there is a demand for a higher data transfer rate of a memory device, and this demand is met by using a synchronous memory device. Examples of the synchronous memory device include an SDRAM (Synchronous Dynamic Random Access Memory).
The SDRAM is operated in synchronism with a system clock (CLK) of the LSI. For example, the SDRAM receives control signals, such as a RAS signal, a CAS signal, and a WE signal, in synchronism with the rising edge of the CLK signal, determines a control command by combining 1 and 0 of these input signals, and further receives an address signal and a data signal as well in synchronism with the rising edge of the CLK signal.
An increased data transfer rate of the above-mentioned memory device causes a problem that to synchronize an input signal with the high-speed CLK signal, a setup time and a hold time of the input signal are shortened. To solve this problem, there has been proposed a technique using a data strobe signal (DQS) that notifies the synchronous memory device of timing at which the input signal, such as an address signal or a data signal, is sent to a first stage circuit thereof, with the aim of enabling the memory device to secure the setup time and the hold time of the input signal. Examples of the memory device using the DQS signal include a DDR(Double Data Rate)2 SDRAM and a DDR3 SDRAM.
Generally, a memory controller is interposed between the above-mentioned memory device and a CPU to adjust the timing of writing and reading data based on a result of printed circuit board simulation by taking into account the arrangement of wiring on a printed circuit board on which the memory device and other components are mounted.
This memory controller is required to perform timing adjustment with higher accuracy in accordance with the increase in the speed of the CLK signal based on which it performs synchronization, and further is required to perform timing adjustment by taking into account processing accuracy variation caused by LSI miniaturization, lowered power supply voltage of the internal circuit of the LSI for reduced power consumption of the LSI, and variation in delay time of input/output buffers which vary with the temperature of the printed circuit board and other factors. In addition, to absorb variation in delay time which varies with the difference between individual input/output buffers, it is necessary to adjust the delay time after LSI assembly.
For example, to write and read data in and from a high-speed memory device, the memory controller is required to perform appropriate timing adjustment particularly for a circuit part that holds read data output from the memory device in an internal flip-flop, a circuit part that synchronizes the read data held in this flip-flop with the CLK signal, and so forth.
The memory controller calculates a round trip delay which is a time period taken for a CLK signal output from the memory controller to return to the memory controller by way of the memory device, as a DQS signal, so as to determine an effective range of read data synchronized with the CLK signal.
When the memory controller is a DDR3 SDRAM, it has a write leveling function and a read leveling function for adjusting write/read access timing, according to JEDEC specifications.
In the write leveling function, when write leveling enable of an MR1 register of the memory device is set to 1, the memory controller outputs a value of a skew between the CLK and DQS signals. More specifically, the memory device samples the CLK signal at a rising edge of the DQS signal issued by the memory controller, and returns 1 to a data signal (DQ) synchronized with the DQS signal. The memory controller gradually changes the phase difference between the CLK and DQS signals, and adjusts timing based on the result of the DQ signal such that the maximum margin in timing can be provided (see FIGS. 17A and 17B).
FIGS. 17A and 17B are timing diagrams of the CLK and DQS signals in each of the memory controller and the memory device, in which FIG. 17A shows signals before the memory controller performs timing adjustment, and FIG. 17B shows the signals after the memory controller has performed timing adjustment.
Referring to FIG. 17A, in a case where the memory controller outputs the DQS signal in a manner synchronizing the rising timing of the DQS signal with the rising timing of the CLK signal, the CLK and DQS signals in the memory device are different in rising timing due to influence of wiring length, wiring load, and the like, whereby the memory device cannot sample the CLK signal at the rising edge of the DQS signal, and hence the memory device returns 0 to the DQ signal. Further, the memory controller shifts the output timing of the DQS signal from that of the CLK signal to thereby search for a point at which the DQ signal is changed from 0 to 1 as shown in FIG. 17B. When the memory device returns 1 to the DQ signal, this indicates that the CLK signal has been sampled at the rising edge of the DQS signal.
On the other hand, in the read leveling function, when the memory controller is set as an MPR (Multipurpose Register), the memory device holds and outputs a predetermined data pattern, whereby the memory controller is made capable of knowing timing for receiving the data pattern, and hence the memory controller can adjust latency between the issuing of a read command and the return of read data after the issuing of the read command.
In read access, the memory device outputs the DQS signal, and the memory controller detects the number of cycles from the issuing of the read command to the receiving of data, and gradually shifts the timing of reading the read data from the timing at which the DQS signal is internally detected, to thereby detect the optimum point of change so as to adjust the skew value between the CLK and DQS signals.
Further, the memory controller improves signal quality by issuing a ZQ calibration command to perform correction dependent on PVT (process, voltage, and temperature) changes occurring during operation, and also by ODT (On Die Termination).
However, execution of calibration at the startup of the apparatus or during operation by the memory controller affects data transfer between the memory device and the CPU, which causes a problem that the performance is degraded.
To solve this problem, it has been envisaged to set parameters using a calibration method adapted to environmental changes occurring within an apparatus (for example, see PTL 1 below).
In the technique disclosed in PTL 1, unless there is a large change in temperature measured at every preset time or at predetermined time intervals, the calibration time is reduced by executing calibration in a simplified manner or by using a preset value stored in the memory device.
On the other hand, information apparatuses, including cellular phones and smart phones, have been made increasingly multifunctional, and this causes a serious problem of increased power consumption of an LSI in these information apparatuses.
For this reason, there is a demand for designing memory devices incorporated in the LSI in a manner adapted to low-power consumption by shifting some of the memory devices to a sleep mode or turning off some of the memory devices.
In a case where some of the memory devices are turned off, volatile memory devices cannot hold data without power supply, and hence it is necessary to save data to a nonvolatile memory device which can hold data even after interruption of power. This causes a problem that when a memory device is powered off for an energy saving mode of the LSI, it takes execution time to save the data stored therein in the nonvolatile memory device.
To solve this problem, there has been developed, for example, an MRAM (Magnetoresistive Random Access Memory) which is a nonvolatile memory device, as an alternative to the volatile memory device, such as a DDR3.
The MRAM is capable of performing high-speed communication, and further, magnetically holding data even after the memory device is powered off, and hence the data is not required to be saved in another nonvolatile memory device differently from the above-mentioned volatile memory device. Therefore, even when the memory device is powered off for the energy saving mode of the LSI, it is possible to eliminate the time required for saving the data in another memory device.
To this end, there has been proposed a technique that makes it possible to realize high-speed start by storing a startup program in the MRAM at the first time of power on, and executing the startup program stored in the MRAM at each subsequent time of power on.